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MK1574 - Frame Rate Communications PLL

Datasheet Summary

Description

The MK1574-01 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 kHz clock input as a reference, and generates many popular communications frequencies.

All outputs are frequency locked together and to the input.

Features

  • Packaged in 16 pin narrow (150 mil) SOIC.
  • Exact multiplications stored in the device eliminate the need for external dividers.
  • Accepts 8 kHz input clock.
  • Output clock rates include T1, E1, T2, E2.
  • 3.0V to 5.5V operation.
  • Available in commercial (0 to +70 C) or industrial (-40 to +85 C) temperature ranges.
  • For jitter attenuation, use the MK2049 Block Diagram VDD GND 2 2 Output Buffer Output Buffer Output Buffer Output Buffer CLK1.

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Datasheet preview – MK1574

Datasheet Details

Part number MK1574
Manufacturer Integrated Circuit Systems
File Size 83.70 KB
Description Frame Rate Communications PLL
Datasheet download datasheet MK1574 Datasheet
Additional preview pages of the MK1574 datasheet.

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Full PDF Text Transcription

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I C R O C LOC K MK1574 Frame Rate Communications PLL Description The MK1574-01 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 kHz clock input as a reference, and generates many popular communications frequencies. All outputs are frequency locked together and to the input. This allows for the generation of locked clocks to the 8 kHz backplane clock, simplifying clock generation and distribution in communications systems. MicroClock can customize this device for any other different frequencies. Features • Packaged in 16 pin narrow (150 mil) SOIC • Exact multiplications stored in the device eliminate the need for external dividers • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • 3.0V to 5.
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