PA7140 Datasheet PDF | Integrated Circuit Technology

Integrated Circuit Technology PA7140

The PA7140 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on ICT’s CMOS EEPROM technology. The PA7140 offers a versatile logic array architecture with 24 I/O pins, 14 input pins and 60 registers/latches (24 buried logic cells, 12 input registers/latches, 24 buried I/O registers/latches). Its logic array implements 100 sum-of-products logic functions divided into two groups each serving 12 logic cells.

Part No.	PA7140
Datasheet	PA7140 Download
Manufacturer	Integrated Circuit Technology
Description	Programmable Electrically Erasable Logic Array
Buy	Stock & Price

FEATURES

s Programmable Electrically Erasable Logic Array s Versatile Logic Array Architecture - 24 I/Os, 14 inputs, 60 registers/latches - Up to 72 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried High-Speed Commercial and Industrial Versions - As fast as 13ns/20ns (tpdi/tpdx), 66.6MHz (fMAX) - Industrial grade available for 4.5 to 5.5V Vcc and -40 to +85 °C temperatures Ideal for Combinatorial, Synchronous and Asynchronous Logic

APPLICATIONS

- Integration of multiple PLDs and random logic - Buried counters, complex state-machines - Comparators, decoders, other wide-gate functions CMOS Electrically Erasable Technology , - Reprogrammable in 40-pin DIP 44-pin PLCC, and TQFP packages Flexible Logic Cell - Up to 3 output functions per logic cell - D,T and JK registers with special features - Independent or global clocks, resets, presets, clock polarity and output enables - Sum-of-products logic for output enables...