IDT72V3670 Datasheet | Integrated Device Tech

among the following memory organizations:mercial IDT72V3640  1,024 x 36 IDT72V3650  2,048 x 36 IDT72V3660  4,096 x 36 IDT72V3670  8,192 x 36 IDT72V3680  16,384 x 36 IDT72V3690  32,768 x 36 IDT72V36100  65,536 x 36 IDT72V36110  131,072 x 36 133 MHz operation (7.5 ns read/write cycle time) User selectable input and output port bus-sizing - x36 in to x36 out - x36 in to x18 out - x36 in to x9 out - x18 in to x36 out - x9 in to x36 out Big-Endian/Little-Endian user selectable byte representation 5V input tolerant Fixed, low first word latency Zero latency retransmit Auto power down minimizes standby power consumption Master Reset clears entire FIFO Partial Reset clears data, but retains programmable settings Empty, Full and Half-Full flags signal FIFO status Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets Selectable synchronous/asynchronous timing modes for Almost Empty and Almost-Full flags Program programmable flags by either serial or parallel means Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) Output enable puts data outputs into high impedance state Easily expandable in depth and width Independent Read and Write Clocks (permit reading and writing simultaneously) Available in the 128-pin Thin Quad Flat Pack (TQFP) High-performance submicron CMOS technology Industrial temperature range (- 40°C to +85°C) is available FUNCTIONAL BLOCK DIAGRAM D0 -Dn (x36, x18 or x9) WEN WCLK LD SEN INPUT REGISTER OFFSET REGISTER FF/IR PAF EF/OR PAE HF FWFT/SI PFM FSEL0 FSEL1 WRITE CONTROL LOGIC FLAG LOGIC RAM ARRAY 1,024 x 36, 2,048 x 36 4,096 x 36, 8,192 x 36 16,384 x 36, 32,768 x 36 65,536 x 36, 131,072 x36 WRITE POINTER READ POINTER BE IP BM IW OW MRS PRS CONTROL LOGIC BUS CONFIGURATION RESET LOGIC OUTPUT REGISTER READ CONTROL LOGIC RT RM RCLK REN Q0 -Qn (x36, x18 or x9) 4667 drw 01 The Super Sync II FIFO is a trademark and the IDT logo...