79RC32K438 - Communications Processor

Product Overview

Integrated Device Technology

Part number	79RC32K438
Manufacturer	Integrated Device Technology
File Size	714.94 KB
Description	Communications Processor
Datasheet	79RC32K438 Datasheet
Additional preview pages of the 79RC32K438 datasheet.

for EJTAG/JTAG pins in Table 1.

Changed DDRDM[7:0] from input/output to output only in Tables 1 and 2 and Logic Diagram.

Added new section, Voltage Sense Signal Timing, as part of EJTAG description.

32-bit CPU Core.
MIPS32 instruction set.
Cache Sizes: 16KB instruction and data caches, 4-Way set associative, cache line locking, non-blocking prefetches.
16 dual-entry JTLB with variable page sizes.
3-entry instruction TLB www. DataSheet4U. com.
3-entry data TLB.
Max issue rate of one 32x16 multiply per clock.
Max issue rate of one 32x32 multiply every other clock.
CPU control with start, stop and single stepping.
S.

Other Datasheets by Integrated Device Technology

Published: Sep 19, 2008 |