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8V41N010 Datasheet PDF

Integrated Device Technology 8V41N010

The 8V41N010 is a PLL-based clock generator specifically designed for Cavium Networks Octeon II processors. This high performance device is optimized to generate the processor core reference clock, the PCI-Express, sRIO, XAUI, SerDes reference clocks and the clocks for both the Gigabit Ethernet MAC and PHY. The output frequencies are generated from a 25MHz external input source or an external 25MHz parallel resonant crystal.
Part No. 8V41N010
Datasheet 8V41N010 Download
Manufacturer
Integrated Device Technology
Description Clock Generator
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8V41N010 datasheet page 1 preview

GENERAL DESCRIPTION

The industrial temperature range of the 8V41N010 supports telecommunication, networking, and storage requirements. Pin Assignment DATA SHEET

FEATURES

● Eight selectable 100MHz and 156.25MHz clocks for PCI Express, sRIO and GbE, HCSL interface levels
● One single-ended QF LVCMOS/LVTTL clock output at 50MHz
● Selectable external crystal or differential (single-ended) input source
● Crystal oscillator interface designed for 25MHz, parallel resonant crystal
● Differential CLK, nCLK input pair that can accept: LVPECL, LVDS, LVHSTL, HCSL input levels
● Internal resistor bias on nCLK pin allows the user to drive CLK input with external single-ended (LVCMOS/ LVTTL) input levels
● Full 3.3V supply mode
● -40°C to 85°C ambient operating temperature
● Lead-free (RoHS 6) packaging VDDO_QE IREF OE_D GND nc nc nQD0 QD0 VDDO_QD VDD OE_C GND nQC1 QC1 nQC0 QC0 VDDO_QC OE_B QE0 nQE0 QE1 nQE1 GND OE_E nc FSEL_C1 GND VDDA nc FSEL_D1 VDD nMR VDDO nc GND nc 54 53 52 51 50 49 48 47 46 45...
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