AN-136 Datasheet | Integrated Device Technology

features to significantly ease the design of high performance cache subsystems for today’s high speed processors. These Tag RAMs are designed for easy interfacing to Intel and Power PC processors, but are very flexible and can easily be used in other applications as well. This application note first provides some background information on caches, then describes in detail the architecture and operation of the 71215 and 71216. This is followed by three application examples, then a brief discussion of cache coherency protocol implementation using these Tag RAMs. Since the 71215 and 71216 are very similar, the descriptions and explanations in this application note apply to both unless otherwise noted. CACHE AND TAG BASICS For those new to caches, a brief review of cache basics may be worthwhile. A cache is a memory that provides a CPU with high speed access to a subset of the data from main memory. Our discussions are focused on the secondary cache, which is also known as the L2 cache, but it is not much different from the faster primary (L1) cache residing inside most CPUs. The cache consists of a controller, a data memory and a tag memory. The purpose of the data memory is to store the active data from main memory, and is posed of either synchronous burst or asynchronous SRAMs. The tag memory stores indexes (part of the CPU address field) that indicate which data is stored in the cache. Additionally, most caches also require at least one bit of memory for each cache entry, to indicate the valid or dirty status of that entry. Figure 1 shows how the CPU address field relates to the cache and the tag memory. This example includes valid and dirty status bits, and represents a 512KB cache, 2GB cacheable address space, 32-byte line size, and 8-byte word size. DATA SRAM ADDRESS A31 MSB A30 A19 A18 A5 A4 A3 LSB TAG MEMORY 12 1 1 TAG ADDRESS LINE VALID LINE DIRTY PARATOR MATCH to CACHE CONTROLLER 3176 drw 01 Figure 1. CPU Address Field and the L2 Cache...