Integrated Device Technology ICS9LPR501
The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus.| Part No. | ICS9LPR501 |
|---|---|
| Datasheet | ICS9LPR501 Download |
| Manufacturer |  Integrated Device Technology |
| Description | 64-pin CK505 w/Fully Integrated Voltage Regulator |
| Buy | Stock & Price |
FEATURES
:● 2 - CPU differential low power push-pull pairs
● 10 - SRC differential low power push-pull pairs
● 1 - CPU/SRC selectable differential low power push-pull pair
● 1 - SRC/DOT selectable differential low power push-pull pair
● 5 - PCI, 33MHz
● 1 - PCI_F, 33MHz free running
● 1 - USB, 48MHz
● 1 - REF, 14.318MHz Key Specifications:
● CPU outputs cycle-cycle jitter < 85ps
● SRC output cycle-cycle jitter < 125ps
● PCI outputs cycle-cycle jitter < 250ps
● +/- 100ppm frequency accuracy on CPU & SRC clocks
FEATURES
/Benefits:● Does not require external pass transistor for voltage regulator
● Supports spread spectrum modulation, default is 0.5% down spread
●
● Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning Selectable between one SRC differential push-pull pair and two single-ended outputs Pin Configuration PCI0/CR#_A VDDPCI PCI1/CR#_B PCI2/TME PCI3 PCI4/SRC5_EN PCI_F5/ITP_EN GNDPCI VDD48 USB_48MHz/FSLA GND48 VDD96_IO DOTT_96/SRCT0 DOTC_9...
