IDT7034S Datasheet | Integrated Device Technology

HIGH-SPEED 4K x 18 DUAL-PORT STATIC RAM Features : x x IDT7034S/L x x x True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access — mercial: 15/20ns (max.) Low-power operation — IDT7034S Active: 850m W (typ.) Standby: 5m W (typ.) — IDT7034L Active: 850m W (typ.) Standby: 1m W (typ.) Separate upper-byte and lower-byte control for multiplexed bus patibility IDT7034 easily expands data bus width to 36 bits or more x x x x x x x x x using the Master/Slave select when cascading more than one device M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port Battery backup operation—2V data retention TTL-patible, single 5V (±10%) power supply Available in 100-pin Thin Quad Flatpack Industrial temperature range (–40°C to +85°C) is available for selected speeds Functional Block Diagram R/WL R/WR LBL CEL OEL LBR CER OER I/O9L-I/O17L I/O0L-I/O8L BUSYL (1,2) I/O Control I/O Control I/O9R-I/O17R I/O0R-I/O8R BUSYR (1,2) . A11L A0L Address Decoder MEMORY ARRAY Address Decoder A11R A0R CEL OEL R/WL SEML (2) INTL ARBITRATION INTERRUPT SEMAPHORE LOGIC CER OER R/WR SEMR (2) INTR 4089 drw 01 M/S NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated...