IDT707288S Datasheet | Integrated Device Technology

Integrated Device Technology, Inc. HIGH-SPEED 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS DESCRIPTION: ADVANCED IDT707288S/L Features : - 64K x 16 Bank-Switchable Dual-Ported SRAM Architecture - Four independent 16K x 16 banks - 1 Megabit of memory on chip - Fast asynchronous address-to-data access time: 20ns - User-controlled input pins included for bank selects - Independent port controls with asynchronous address & data busses - Four 16-bit mailboxes available to each port for interprocessor munications; interrupt option - Interrupt flags with programmable masking - Dual Chip Enables allow for depth expansion without external logic - UB and LB are available for bus matching to x8 or x16 busses; also support very fast banking - TTL-patible, single 5V (±10%) power supply - Available in a 100-pin Thin Quad Plastic Flatpack (TQFP) and a 108-pin ceramic Pin Grid Array (PGA) The IDT707288 is a high-speed 64K x 16 (1M bit) Bank Switchable Dual-Ported SRAM organized into four independent 16K x 16 banks. The device has two independent ports with separate controls, addresses, and I/O pins for each port, allowing each port to asynchronously access any 16K x 16 memory block not already accessed by the other port. Accesses by the ports into specific banks are controlled via bank select pin inputs under the user's control. Mailboxes are provided to allow inter-processor munications. Interrupts are provided to indicate mailbox writes have occurred. An automatic power down feature controlled by the chip enables (CE0 and CE1) permits the on-chip circuitry of each port to enter a very low standby power mode and allows fast depth expansion. The IDT707288 offers a maximum address-to-data access time as fast as 20ns, while typically operating on only 900m W of power, and is available in a 100-pin Thin Quad Plastic Flatpack (TQFP) and a 108-pin ceramic Pin Grid Array (PGA). R/ FUNCTIONAL BLOCK DIAGRAM R/ L 0L CE1L L L L CONTROL...