IDT70V24L Overview
Key Features
- True Dual-Ported memory cells which allow simultaneous access of the same memory location
- High-speed access
- Commercial: 25/35/55ns (max.)
- Low-power operation
- Separate upper-byte and lower-byte control for multiplexed bus compatibility
- IDT70V24 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device
- M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave
- Busy and Interrupt Flags
- Devices are capable of withstanding greater than 2001V electrostatic charge
- On-chip port arbitration logic
