IDT70V3399S Overview
The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times.
IDT70V3399S Key Features
- Due to limited pin count, JTAG is not supported on the 128-pin TQFP package
- mercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
- Industrial: 4.2ns (133MHz) (max.) Selectable Pipelined or Flow-Through output mode
- Due to limited pin count PL/FT option is not supported on the 128-pin TQFP package. Device is pipelined outputs only on
- 6ns cycle time, 166MHz operation (6Gbps bandwidth)
- Fast 3.6ns clock to data out
- 1.7ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 166MHz
- Functional Block Diagram
- I/O17L
- I/O17R
