IDT70V38L Datasheet | Integrated Device Technology

.. HIGH-SPEED 3.3V 64K x 18 DUAL-PORT STATIC RAM Features - - - - - True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed access - mercial: 15/20ns (max.) - Industrial: 20ns (max.) Low-power operation - IDT70V38L Active: 440m W (typ.) Standby: 660µW (typ.) Dual chip enables allow for depth expansion without external logic IDT70V38 easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device - - - - - - - - - M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave Busy and Interrupt Flags On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port Separate upper-byte and lower-byte controls for multiplexed bus and bus matching patibility LVTTL-patible, single 3.3V (±0.3V) power supply Available in a 100-pin TQFP Industrial temperature range (- 40°C to +85°C) is available for selected speeds Functional Block Diagram R/WL UBL CE0L CE1L OEL LBL R/WR UBR CE0R CE1R OER LBR I/O 9-17L I/O 0-8L BUSYL (1,2) A15L A0L 64Kx18 MEMORY ARRAY 70V38 16 16 I/O9-17R I/O Control I/O Control I/O0-8R BUSYR A15R A0R (1,2) . Address Decoder Address Decoder CE0L CE1L OEL R/WL SEML INT L (2) ARBITRATION INTERRUPT SEMAPHORE LOGIC CE0R CE1R OER R/WR SEMR (2) INTR 4850 drw 01 M/S (1) NOTES: 1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH). 2. BUSY and INT are non-tri-state totem-pole outputs...