IDT71V2546SA Description
The IDT71V2546/48 are 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAMS. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBTTM, or Zero Bus Turnaround.
IDT71V2546SA Key Features
- 150 MHz (3.8 ns Clock-to-Data Access) ZBTTM Feature
- No dead cycles between write and read cycles Internally synchronized output buffer enable eliminates the need to control
IDT71V2546SA Applications
- BW4) control (May tie active) Three chip enables for simple depth expansion 3.3V power supply (±5%), 2.5V I/O Supply (VDDQ) Optional Boundary Scan JTAG Interfac