IDT71V2578SA Overview
The IDT71V2576/78 are high-speed SRAMs organized as 128K x 36/256K x 18. The IDT71V2576/78 SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to generate a selftimed write based upon a decision which can be left until the end of the write cycle.
IDT71V2578SA Key Features
- 150MHz 3.8ns clock access time
- 133MHz 4.2ns clock access time LBO input selects interleaved or linear burst mode Self-timed write cycle with global wri
- Boundary Scan JTAG Interface (IEEE 1149.1 pliant) Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack (TQFP)
