IDT71V432 Datasheet | Integrated Device Technology

32K x 32 Cache RAM™ 3.3V Synchronous SRAM Burst Counter Single Cycle Deselect Features x x IDT71V432 x x x x x x 32K x 32 memory configuration Supports high-performance system speed: mercial and Industrial: - 5ns Clock-to-Data Access (100MHz) - 6ns Clock-to-Data Access (83MHz) - 7ns Clock-to-Data Access (66MHz) Single-cycle deselect functionality (patible with Micron Part # MT58LC32K32D7LG-XX) LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) Power down controlled by ZZ input Operates with a single 3.3V power supply (+10/-5%) Packaged in a JEDEC Standard 100-pin rectangular plastic thin quad flatpack (TQFP). Description The IDT71V432 is a 3.3V high-speed 1,048,576-bit Cache RAM organized as 32K x 32 with full support of the Pentium™ and Power PC™ processor interfaces. The pipelined burst architecture provides costeffective 3-1-1-1 secondary cache performance for processors up to 100 MHz. The IDT71V432 Cache RAM contains write, data, address, and control registers. Internal logic allows the Cache RAM to generate a selftimed write based upon a decision which can be left until the extreme end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V432 can provide four cycles of data for a single address presented to the Cache RAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge. If burst mode operation is selected (ADV=LOW), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses will be defined by the internal burst counter and the LBO input pin. The IDT71V432 Cache RAM utilizes IDT's high-performance, highvolume 3.3V CMOS...