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IDT71V65803 - 3.3V Synchronous ZBT SRAMs

This page provides the datasheet information for the IDT71V65803, a member of the IDT-71V 3.3V Synchronous ZBT SRAMs family.

Datasheet Summary

Description

The IDT71V65603/5803 are 3.3V high-speed 9,437,184-bit (9 Megabit) synchronous SRAMS.

They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads.

Thus, they have been given the name ZBTTM, or Zero Bus Turnaround.

Features

  • 256K x 36, 512K x 18 memory configurations Supports high performance system speed - 150MHz (3.8ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized output buffer enable eliminates the need to control OE Single R/W (READ/WRITE) control pin Positive clock-edge triggered address, data, and control signal registers for fully pipelined.

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Datasheet preview – IDT71V65803

Datasheet Details

Part number IDT71V65803
Manufacturer Integrated Device Technology
File Size 391.44 KB
Description 3.3V Synchronous ZBT SRAMs
Datasheet download datasheet IDT71V65803 Datasheet
Additional preview pages of the IDT71V65803 datasheet.

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Full PDF Text Transcription

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256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs x x x x x x x x x x x x x IDT71V65603 IDT71V65803 Features 256K x 36, 512K x 18 memory configurations Supports high performance system speed - 150MHz (3.8ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized output buffer enable eliminates the need to control OE Single R/W (READ/WRITE) control pin Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications 4-word burst capability (interleaved or linear) Individual byte write (BW1 - BW4) control (May tie active) Three chip enables for simple depth expansion 3.3V power supply (±5%) 3.
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