IDT72125 Datasheet | Integrated Device Technology

CMOS PARALLEL-TO-SERIAL FIFO 1,024 x 16 Features : - 25ns parallel port access time, 35ns cycle time - 50MHz serial shift frequency - Wide x16 organization offering easy expansion - Low power consumption (50m A typical) - Least/Most Significant Bit first read selected by asserting the FL/DIR pin - Four memory status flags: Empty, Full, Half-Full, and Almost- Empty/Almost-Full - Dual-Port zero fall-through architecture - Available in 28-pin 300 mil plastic DIP and 28-pin SOIC - Green parts available, see ordering information DESCRIPTION: The IDT72125 is a high-speed, low- power, dedicated, parallel-to-serial FIFO. This FIFO Features a 16-bit parallel input port and a serial output port with 1,024 word depths, respectively. The ability to buffer wide word widths (x16) make these FIFOs ideal for laser printers, FAX machines, local area networks (LANs), video storage and disk/ tape controller applications. Expansion in width and depth can be achieved using multiple chips. IDT’s unique serial expansion logic makes this possible using a minimum of pins. The unique serial output port is driven by one data pin (SO) and one clock pin (SOCP). The Least Significant or Most Significant Bit can be read first by programming the DIR pin after a reset. Monitoring the FIFO is eased by the availability of four status flags: Empty, Full,Half-Fulland Almost-Empty/Almost-Full. The Fulland Emptyflagsprevent any FIFOdataoverfloworunderflowconditions. The Half-Full Flagisavailable in both single and expansion mode configurations. The Almost-Empty/Almost Full Flag is available only in a single device mode. The IDT72125 is fabricated using submicron CMOS technology. FUNCTIONAL BLOCK DIAGRAM RS W D0-15 RESET LOGIC WRITE POINTER RAM ARRAY 1,024 x 16 READ POINTER RSIX RSOX...