Datasheet4U Logo Datasheet4U.com

IDT72T20108 - DDR/SDR FIFO

General Description

The IDT72T2098/72T20108/72T20118/72T20128 are exceptionally deep, extremely high speed, CMOS First-In-First-Out (FIFO) memories with the ability to read and write data on both rising and falling edges of clock.

Key Features

  • Choose among the following memory organizations: IDT72T2098  32,768 x 20/65,536 x 10 IDT72T20108  65,536 x 20/131,072 x 10 IDT72T20118  131,072 x 20/262,144 x 10 IDT72T20128  262,144 x 20/524,288 x 10 Up to 250MHz Operation of Clocks - 4ns read/write cycle time, 3.2ns access time Users selectable input port to output port data rates, 500Mb/s Data Rate -DDR to.

📥 Download Datasheet

Datasheet Details

Part number IDT72T20108
Manufacturer Integrated Device Technology
File Size 503.62 KB
Description DDR/SDR FIFO
Datasheet download datasheet IDT72T20108 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com 2.5 VOLT HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION 32,768 x 20/65,536 x 10, 65,536 x 20/131,072 x 10 131,072 x 20/262,144 x 10, 262,144 x 20/524,288 x 10 IDT72T2098, IDT72T20108 IDT72T20118, IDT72T20128 FEATURES: • • • • • • • • • • • • • Choose among the following memory organizations: IDT72T2098  32,768 x 20/65,536 x 10 IDT72T20108  65,536 x 20/131,072 x 10 IDT72T20118  131,072 x 20/262,144 x 10 IDT72T20128  262,144 x 20/524,288 x 10 Up to 250MHz Operation of Clocks - 4ns read/write cycle time, 3.2ns access time Users selectable input port to output port data rates, 500Mb/s Data Rate -DDR to DDR -DDR to SDR -SDR to DDR -SDR to SDR User selectable HSTL or LVTTL I/Os Read Enable & Read Clock Echo outputs aid high speed operation 2.