Datasheet Details
| Part number | IDT72V2105 |
|---|---|
| Manufacturer | Integrated Device Technology |
| File Size | 193.00 KB |
| Description | CMOS FIFO memories |
| Datasheet | IDT72V2105_IntegratedDeviceTechnology.pdf |
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Overview: 3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO™ 131,072 x 18 262,144 x 18 .EATURES: • • • • • • • IDT72V295 IDT72V2105 • • • • • • • • • • • Choose among the following memory organizations: IDT72V295 131,072 x 18 IDT72V2105 262,144 x 18 Pin-patible with the IDT72V255/72V265 and the IDT72V275/ 72V285 SuperSync FIFOs 10ns read/write cycle time (6.
| Part number | IDT72V2105 |
|---|---|
| Manufacturer | Integrated Device Technology |
| File Size | 193.00 KB |
| Description | CMOS FIFO memories |
| Datasheet | IDT72V2105_IntegratedDeviceTechnology.pdf |
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: The IDT72V295/72V2105 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls.
These FIFOs offer numerous improvements over previous SuperSync FIFOs, including the following: • The limitation of the frequency of one clock input with respect to the other has been removed.
The Frequency Select pin (FS) has been removed, .UNCTIONAL BLOCK DIAGRAM WEN WCLK D0 -D17 LD SEN INPUT REGISTER OFFSET REGISTER FF/IR PAF EF/OR PAE HF FWFT/SI WRITE CONTROL LOGIC RAM ARRAY 131,072 x 18 262,144 x 18 FLAG LOGIC WRITE POINTER READ POINTER OUTPUT REGISTER MRS PRS READ CONTROL LOGIC RT RESET LOGIC RCLK REN OE Q0 -Q17 4668 drw 01 The SuperSync FIFO is a trademark and the IDT logo is a registered tra
| Part Number | Description |
|---|---|
| IDT72V211 | FIFO memories |
| IDT72V215 | FIFO memories |
| IDT72V201 | FIFO memories |
| IDT72V205 | FIFO memories |
| IDT72V275 | CMOS FIFO memories |
| IDT72V281 | CMOS FIFO memories |
| IDT72V285 | CMOS FIFO memories |
| IDT72V291 | CMOS FIFO memories |
| IDT72V01 | 3.3 VOLT CMOS ASYNCHRONOUS FIFO |
| IDT72V02 | 3.3 VOLT CMOS ASYNCHRONOUS FIFO |