IDT72V281 Datasheet | Integrated Device Technology

3.3 VOLT CMOS SuperSync FIFO™ 65,536 x 9 131,072 x 9 .EATURES: - - - - - .. IDT72V281 IDT72V291 - - - - - - - - - - - - - Choose among the following memory organizations: IDT72V281 65,536 x 9 IDT72V291 131,072 x 9 Pin-patible with the IDT72V261/72V271 SuperSync FIFOs 10ns read/write cycle time (6.5ns access time) Fixed, low first word data latency time Auto power down minimizes standby power consumption Master Reset clears entire FIFO Partial Reset clears data, but retains programmable settings Retransmit operation with fixed, low first word data latency time Empty, Full and Half-Full flags signal FIFO status Programmable Almost-Empty and Almost-Full flags, each...