IDT72V3683 Datasheet | Integrated Device Technology

Features - - - - - - - Memory storage capacity: IDT72V3683 - 16,384 x 36 IDT72V3693 - 32,768 x 36 IDT72V36103 - 65,536 x 36 Clock frequencies up to 100 MHz (6.5 ns access time) Clocked FIFO buffering data from Port A to Port B IDT Standard timing (using EF and FF) or First Word Fall Through Timing (using OR and IR flag functions) Programmable Almost-Empty and Almost-Full flags; each has five default offsets (8, 16, 64, 256 and 1,024) Serial or parallel programming of partial flags Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits (byte) - - - - - - - - - - Big- or Little-Endian format for word and byte bus sizes Retransmit Capability Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings Mailbox bypass registers for each FIFO Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) Easily expandable in width and depth Auto power down minimizes power dissipation Available in a space-saving 128-pin Thin Quad Flatpack (TQFP) Pin patible with the lower density parts, IDT72V3623/ 72V3633/72V3643/72V3653/72V3663/72V3673 Industrial temperature range (- 40°C to +85°C) is available FUNCTIONAL BLOCK DIAGRAM MBF1 Mail 1 Register Port-A Control Logic CLKA CSA W/RA ENA MBA RS1 RS2 PRS Bus Matching Input Register Output Register FIFO1 Mail1, Mail2, Reset Logic RAM ARRAY 16,384 x 36 32,768 x 36 65,536 x 36 RT RTM FIFO Retransmit Logic Write Pointer Read Pointer B0-B35 A0-A35 FF/IR AF Status Flag...