IDT74ALVCH16823 Datasheet | Integrated Device Technology

IDT74ALVCH16823 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE .. 3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD - 0.5 MICRON CMOS Technology - Typical t SK(o) (Output Skew) < 250ps - ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200p F, R = 0) - VCC = 3.3V ± 0.3V, Normal Range - VCC = 2.7V to 3.6V, Extended Range - VCC = 2.5V ± 0.2V - CMOS power levels (0.4µ W typ. static) - Rail-to-Rail output swing for increased noise margin - Available in TSSOP package Features : DRIVE Features : - High Output Drivers: ±24m A - Suitable for heavy loads APPLICATIONS: - 3.3V high speed systems - 3.3V and lower voltage puting systems This 18-bit bus-interface flip-flop is built using advanced dual metal CMOS technology. The ALVCH16823 Features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. The ALVCH16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN) input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN high disables the clock buffer, thus latching the outputs. Taking the clear (CLR) input low causes the Q outputs to go low independently of the clock. A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup ponents. The OE input does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered...