IDT8SLVD1204I Datasheet PDF - Integrated Device Technology LVDS Output Fanout Buffer Specs

IDT8SLVD1204I - LVDS Output Fanout Buffer

Datasheet Summary

Description

The IDT8SLVD1204I is a high-performance differential LVDS fanout buffer.

The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals.

The IDT8SLVD1204I is characterized to operate from a 2.5V power supply.

Features

Four low skew, low additive jitter LVDS output pairs.
Two selectable differential clock input pairs.
Differential PCLK, nPCLK pairs can accept the following differential input levels: LVDS, LVPECL.
Maximum input clock frequency: 2GHz.
LVCMOS/LVTTL interface levels for the control input select pin.
Output skew: 20ps (maximum).
Propagation delay: 300ps (maximum).
Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V, 10k.

Datasheet Details

Part number	IDT8SLVD1204I
Manufacturer	Integrated Device Technology
File Size	561.52 KB
Description	LVDS Output Fanout Buffer
Datasheet	IDT8SLVD1204I Datasheet
Additional preview pages of the IDT8SLVD1204I datasheet.

📁 Similar Datasheet

IDT8SLVD1208-33I - LVDS Output Fanout Buffer (IDT)

IDT8SLVD1208I - LVDS Output Fanout Buffer (IDT)

IDT8SLVP1102I - LVPECL Output Fanout Buffer (IDT)

IDT8SLVP1104I - LVPECL Output Fanout Buffer (Renesas)

IDT8SLVP1104I - LVPECL Output Fanout Buffer (IDT)

IDT8SLVP1212I - LVPECL Output Fanout Buffer (IDT)

IDT8SLVP2102I - LVPECL Output Fanout Buffer (IDT)

IDT8SLVP2108I - LVPECL Output Fanout Buffer (IDT)

IDT821024 - QUAD NON-PROGRAMMABLE PCM CODEC (Integrated Device)

IDT821034 - QUAD PCM CODEC (Integrated Device)

Full PDF Text Transcription

Click to expand full text

2:4, LVDS Output Fanout Buffer, 2.5V IDT8SLVD1204I DATA SHEET General Description The IDT8SLVD1204I is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The IDT8SLVD1204I is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the IDT8SLVD1204I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and four low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

Published: Jan 27, 2016 |