RC32434 Key Features
- MIPS32 instruction set
- Cache Sizes: 8KB instruction and data caches, 4-Way set associative, cache line locking, non-blocking prefetches
- 16 dual-entry JTLB with variable page sizes
- 3-entry instruction TLB
- 3-entry data TLB
- Max issue rate of one 32x16 multiply per clock
- Max issue rate of one 32x32 multiply every other clock
- CPU control with start, stop, and single stepping
- Software breakpoints support
- Hardware breakpoints on virtual addresses