IDT5T9050 Overview
Optimized for 2.5V LVTTL Guaranteed Low Skew < 25ps (max) Very low duty cycle distortion < 300 (max) High speed propagation delay < 1.8ns. (max) Up to 200MHz operation Very low CMOS power levels Hot insertable and over-voltage tolerant inputs 1:5 fanout buffer 2.5V VDD Available in TSSOP package The IDT5T9050 2.5V single data rate (SDR) clock buffer is a single-ended input to five single-ended outputs buffer built...
IDT5T9050 Key Features
- Clock and signal distribution