IDT74FCT833B Datasheet | Integrated Device

® FAST CMOS PARITY BUS TRANSCEIVER DESCRIPTION: IDT54/74FCT833A IDT54/74FCT833B Integrated Device Technology, Inc. Features : - Equivalent to AMD’s Am29833 bipolar parity bus transceiver in pinout/function, speed and output drive over full temperature and voltage supply extremes - High-speed bidirectional bus transceiver for processororganized devices - IDT54/74FCT833A equivalent to Am29833A speed and output drive - IDT54/74FCT833B 30% faster than Am29833A - Buffered direction and three-state controls - Error flag with open-drain output - IOL = 48m A (mercial) and 32m A (military) - TTL input and output level patible - CMOS output level patible - Substantially lower input current levels than AMD’s bipolar Am29800 series (5µA max.) - Available in plastic DIP, CERDIP, LCC and SOIC - Product available in Radiation Tolerant and Radiation Enhanced versions - Military product pliant to MIL-STD-883, Class B The IDT54/74FCT833s are high-performance bus transceivers designed for two-way munications. They each contain an 8-bit data path from the R (port) to the T (port), an 8-bit data path from the T (port) to the R (port), and a 9-bit parity checker/generator. The error flag can be clocked and stored in a register and read at the ERR output. The clear (CLR) input is used to clear the error flag register. The output enables OET and OER are used to force the port outputs to the high-impedance state so that the device can drive bus lines directly. In addition, OER and OET can be used to force a parity error by enabling both lines simultaneously. This transmission of inverted parity gives the designer more system diagnostic capability. The devices are specified at 48m A and 32m A output sink current over the mercial and military temperature ranges, respectively. FUNCTIONAL BLOCK DIAGRAM 8 8 PARITY OE T OE R 8 8 9-BIT PARITY TREE D P CLK CP CLR 2557 drw 01 The IDT logo is a registered trademark of Integrated Device...