IDT8P34S1208I
Overview
The IDT8P34S1208I is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals.
- Eight low skew, low additive jitter LVDS output pairs Two selectable, differential clock input pairs Differential CLK, nCLK pairs can accept the following differential input levels: LVDS, CML Maximum input clock frequency: 1.2GHz (maximum) LVCMOS/LVTTL interface levels for the control input select pin Output skew: 20ps (typical) Propagation delay: 315ps (typical) Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V, 12kHz - 20MHz: 41fs (typical) Full 1.8V supply voltage Lead-free (RoHS 6), 28-Lead VFQFN packaging -40°C to 85°C ambient operating temperature
