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IS61NLF25632 - SRAM

General Description

The 8 Meg 'NF' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for network and communications customers.

Key Features

  • 100 percent bus utilization No wait cycles between Read and Write Internal self-timed write cycle Individual Byte Write Control Single R/W (Read/Write) control pin Clock controlled, registered address, data and control Interleaved or linear burst sequence control using MODE input Three chip enables for simple depth expansion and address p.

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📁 Similar Datasheet

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Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61NLF25636 SRAM
IS61NLF51218 SRAM
IS61NLP25632 256K x 32/ 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM
IS61NLP25636 256K x 32/ 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM
IS61NLP51218 256K x 32/ 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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IS61NF25632 IS61NF25636 IS61NF51218 IS61NLF25632 IS61NLF25636 IS61NLF51218 256K x 32, 256K x 36 and 512K x 18 FLOW-THROUGH 'NO WAIT' STATE BUS SRAM ISSI ® PRELIMINARY INFORMATION APRIL 2001 FEATURES • • • • • • • • • • • • • • • • 100 percent bus utilization No wait cycles between Read and Write Internal self-timed write cycle Individual Byte Write Control Single R/W (Read/Write) control pin Clock controlled, registered address, data and control Interleaved or linear burst sequence control using MODE input Three chip enables for simple depth expansion and address pipelining for TQFP Power Down mode Common data inputs and data outputs CKE pin to enable clock and suspend operation JEDEC 100-pin TQFP, 119 PBGA package Single +3.3V power supply (± 5%) NF Version: 3.