IS43R32800B Datasheet PDF - Integrated Silicon Solution 256Mb DDR Synchronous DRAM PRELIMINARY INFORMATION Specs

IS43R32800B - 256Mb DDR Synchronous DRAM PRELIMINARY INFORMATION

Datasheet Summary

Description

IS43R32800B is a 4-bank x 2,097,152-word x32bit Double Data Rate Synchronous DRAM, with SSTL_2 interface.

All control and address signals are referenced to the rising edge of CLK.

Features

Vdd/Vddq=2.5V+0.2V (-5, -6, -75).
Double data rate architecture; two data transfers per clock cycle.
Bidirectional, data strobe (DQS) is transmitted/ received with data.
Differential clock input (CLK and /CLK).
DLL aligns DQ and DQS transitions with CLK transitions edges of DQS.
Commands entered on each positive CLK edge;.
Data and data mask referenced to both edges of DQS.
4 bank operation controlled by BA0, BA1 (B.

Datasheet Details

Part number	IS43R32800B
Manufacturer	Integrated Silicon Solution
File Size	452.83 KB
Description	256Mb DDR Synchronous DRAM PRELIMINARY INFORMATION
Datasheet	IS43R32800B Datasheet
Additional preview pages of the IS43R32800B datasheet.

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Full PDF Text Transcription

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IS43R32800B 8Mx32 256Mb DDR Synchronous DRAM PRELIMINARY INFORMATION MAY 2008 FEATURES • Vdd/Vddq=2.5V+0.2V (-5, -6, -75) • Double data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data • Differential clock input (CLK and /CLK) • DLL aligns DQ and DQS transitions with CLK transitions edges of DQS • Commands entered on each positive CLK edge; • Data and data mask referenced to both edges of DQS • 4 bank operation controlled by BA0, BA1 (Bank Address) • /CAS latency –2.0/2.5/3.

Published: Jul 25, 2016 |