IS45S16160C Datasheet | ISSI

Description - Single 3.3V ±0.3V power supply - Max. Clock frequency : - 6:166MHz<3-3-3>/-7:143MHz<3-3-3>/-75:133MHz<3-3-3> - Fully synchronous operation referenced to clock rising edge - 4-bank operation controlled by BA0,BA1(Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/FP (programmable) - Burst type- Sequential and interleave burst (programmable) - Byte Control- LDQM and UDQM (IS45S16160C) - Random column access - Auto precharge / All bank precharge controlled by A10 - Auto and self refresh - 8192 refresh cycles /64ms - LVTTL Interface - Package 400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch Pb-free package is available Features Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. - .issi. Rev. B 04/02/09 IS45S83200C IS45S16160C .. CLK CKE /CS /RAS /CAS /WE DQ0-15 : Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O DQM A0-12 BA0,1 Vdd Vdd Q VSS VSSQ : Output Disable / Write Mask : Address Input : Bank Address : Power Supply : Power Supply for Output : Ground : Ground for Output Integrated Silicon Solution, Inc. - .issi. Rev. B 04/02/09 IS45S83200C IS45S16160C .. Note: This figure shows the IS45S83200C. The IS45S16160C configuration is 8192x512x16 of cell array and DQ0-15 Integrated Silicon Solution, Inc. - .issi. Rev. B 04/02/09 IS45S83200C...