IS45S16160D Datasheet | ISSI

FEATURES - Clock frequency: 166, 143 MHz - Fully synchronous; all signals referenced to a positive clock edge - Internal bank for hiding row access/precharge - Single Power supply: 3.3V + 0.3V - LVTTL interface - Programmable burst length - (1, 2, 4, 8, full page) - Programmable burst sequence: Sequential/Interleave - Auto Refresh (CBR) - Self Refresh - 8K refresh cycles every 16 ms (A2 grade) or 64 ms (mercial, industrial, A1 grade) - Random column address every clock cycle - Programmable CAS latency (2, 3 clocks) - Burst read/write and burst read/single write operations capability - Burst termination by burst stop and precharge mand IS42S83200D 54-pin TSOPII IS42S16160D 54-pin TSOPII 8M x 8 x 4 Banks 4M x16x4 Banks 54-ball BGA (contact Marketing) OVERVIEW ISSI's 256Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 256Mb SDRAM is organized as follows. KEY TIMING PARAMETERS Parameter Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 -6 6 10 166 100 5.4 6.5 -7 7 10 143 100 5.4 6.5 -75E Unit - ns 7.5 ns - Mhz 133 Mhz - ns 5.5 ns OPTIONS - Package: 54-pin TSOP-II (x8 and x16) 54-ball BGA (x16 only) - Operating Temperature Range: mercial (0o C to +70o C) Industrial (-40o C to +85o C) Automotive Grade A1 (-40o C to +85o C) Automotive Grade A2 (-40o C to +105o C) - Die Revision: D ADDRESS TABLE Parameter Configuration Refresh Count 32M x 8 8M x 8 x 4 banks ./Ind. 8K/64ms A1 8K/64ms A2 8K/16ms A0-A12 A0-A9 BA0, BA1 A10/AP 16M x 16 4M x 16 x 4 banks 8K/64ms 8K/64ms 8K/16ms A0-A12 A0-A8 BA0, BA1 A10/AP Row Addresses Column Addresses Bank Address Pins Auto Precharge Pins Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to...