IS45S16320B Datasheet | ISSI

FEATURES - Clock frequency: 166, 143, 133 MHz - Fully synchronous; all signals referenced to a positive clock edge - Internal bank for hiding row access/precharge - Power supply Vdd Vddq IS42/45S16320B 3.3V 3.3V IS42S86400B - LVTTL interface - Programmable burst length - (1, 2, 4, 8, full page) - Programmable burst sequence: Sequential/Interleave - Auto Refresh (CBR) - Self Refresh - 8K refresh cycles every 64 ms - Random column address every clock cycle - Programmable CAS latency (2, 3 clocks) - Burst read/write and burst read/single write operations capability - Burst termination by burst stop and precharge mand - Available in 54-pin TSOP-II and 54-ball W-BGA (x16 only) - Operating Temperature Range: mercial: 0o C to +70o C Industrial: -40o C to +85o C Automotive, A1: -40o C to +85o C 3.3V 3.3V OVERVIEW ISSI's 512Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 512Mb SDRAM is organized as follows. IS42S86400B 16Mx8x4 Banks 54-pin TSOPII IS42/45S16320B 8M x16x4 Banks 54-pin TSOPII 54-ball W-BGA KEY TIMING PARAMETERS Parameter Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 -6 6 10 166 100 5.4 6 -7 7 10 143 100 5.4 6 -75E Unit - ns 7.5 ns - Mhz 133 Mhz - ns 5.5 ns Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated...