IS49NLC36160 Overview
1.1 576Mb (64Mx9) mon I/O BGA Ball‐out (Top View) 1 A VREF B VDD C VTT D A221 E A21 F A5 G A8.
IS49NLC36160 Key Features
- 533MHz DDR operation (1.067 Gb/s/pin data rate)
- 38.4Gb/s peak bandwidth (x36 at 533 MHz clock frequency)
- Reduced cycle time (15ns at 533MHz)
- 32ms refresh (16K refresh for each bank; 128K
- 8 internal banks
- Non‐multiplexed addresses (address multiplexing option available)
- SRAM‐type interface
- Programmable READ latency (RL), row cycle time, and burst sequence length
- Balanced READ and WRITE latencies in order to optimize data bus utilization
- Data mask signals (DM) to mask signal of WRITE data; DM is sampled on both edges of DK.