IS49NLC93200 Datasheet PDF - Integrated Silicon Solution 288Mb Common I/O RLDRAM 2 Memory Specs

IS49NLC93200 - 288Mb Common I/O RLDRAM 2 Memory

Datasheet Summary

Description

1.1 288Mb (32Mx9) Common I/O BGA Ball-out (Top View) 1 A VREF B VDD C VTT D A221 E A212 F A5 G A8 H BA2 J NF3 K DK L REF# M WE# N A18 P A15 R VSS T VTT U VDD V VREF 2 VSS DNU4 DNU4 DNU4 DNU4 DNU4 A6 A9 NF3 DK# CS# A16 DNU4 DNU4 DNU4 DNU4 DNU4 ZQ 3 VEXT DNU4 DNU4 DNU4

Features

400MHz DDR operation (800Mb/s/pin data rate).
28.8Gb/s peak bandwidth (x36 at 400 MHz clock frequency).
Reduced cycle time (15ns at 400MHz).
32ms refresh (8K refresh for each bank; 64K refresh command must be issued in total each 32ms).
8 internal banks.
Non-multiplexed addresses (address multiplexing option available).
SRAM-type interface.
Programmable READ latency (RL), row cycle time, and burst sequence length.
Balanced READ and WRITE latencies in.

Datasheet Details

Part number	IS49NLC93200
Manufacturer	Integrated Silicon Solution
File Size	1.32 MB
Description	288Mb Common I/O RLDRAM 2 Memory
Datasheet	IS49NLC93200 Datasheet
Additional preview pages of the IS49NLC93200 datasheet.

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Full PDF Text Transcription

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IS49NLC93200,IS49NLC18160,IS49NLC36800 288Mb (x9, x18, x36) Common I/O RLDRAM 2 Memory JANUARY 2020 FEATURES  400MHz DDR operation (800Mb/s/pin data rate)  28.8Gb/s peak bandwidth (x36 at 400 MHz clock frequency)  Reduced cycle time (15ns at 400MHz)  32ms refresh (8K refresh for each bank; 64K refresh command must be issued in total each 32ms)  8 internal banks  Non-multiplexed addresses (address multiplexing option available)  SRAM-type interface  Programmable READ latency (RL), row cycle time, and burst sequence length  Balanced READ and WRITE latencies in order to optimize data bus utilization  Data mask signals (DM) to mask signal of WRITE data; DM is sampled on both edges of DK.

Published: May 27, 2016 |