IS61DDB41M18A - 18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM

Description

512Kx36 and 1Mx18 configuration available.

On-chip delay-locked loop (DLL) for wide data valid window.

Common I/O read and write ports.

Synchronous pipeline read with late write operation.

Double Data Rate (DDR) interface for read and write input ports.

Fixed 4-b

Integrated Silicon Solution

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Datasheet Details

Part number	IS61DDB41M18A
Manufacturer	Integrated Silicon Solution
File Size	469.90 KB
Description	18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
Datasheet	IS61DDB41M18A Datasheet
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IS61DDB41M18A IS61DDB451236A 1Mx18, 512Kx36 18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM ADVANCED INFORMATION JULY 2012 FEATURES DESCRIPTION  512Kx36 and 1Mx18 configuration available.  On-chip delay-locked loop (DLL) for wide data valid window.  Common I/O read and write ports.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface for read and write input ports.  Fixed 4-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two input clocks (C and C#) for data output control.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5V to1.8V VDDQ, used with 0.75V to 0.9V VREF.

Published: Jul 25, 2016 |