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IS61DDB42M36A - 72Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM

Download the IS61DDB42M36A datasheet PDF. This datasheet also covers the IS61DDB44M18A variant, as both devices belong to the same 72mb ddr-ii (burst 4) cio synchronous sram family and are provided as variant models within a single manufacturer datasheet.

General Description

The 72Mb IS61DDB42M36A and IS61DDB44M18A are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have a common I/O bus.

The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.

Key Features

  • 2Mx36 and 4Mx18 configuration available.
  • On-chip delay-locked loop (DLL) for wide data valid window.
  • Common I/O read and write ports.
  • Synchronous pipeline read with late write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • Fixed 4-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising edges only.
  • Two input clocks (C and C#) for data ou.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61DDB44M18A-IntegratedSiliconSolution.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription for IS61DDB42M36A (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for IS61DDB42M36A. For precise diagrams, and layout, please refer to the original PDF.

IS61DDB44M18A IS61DDB42M36A 4Mx18, 2Mx36 72Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM JANUARY 2015 FEATURES  2Mx36 and 4Mx18 configuration available.  On-chip delay-locke...

View more extracted text
TURES  2Mx36 and 4Mx18 configuration available.  On-chip delay-locked loop (DLL) for wide data valid window.  Common I/O read and write ports.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface for read and write input ports.  Fixed 4-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two input clocks (C and C#) for data output control.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5V to1.8V VDDQ, used with 0.75V to 0.9

More Datasheets from ISSI (now Infineon)

Part Number Description
IS61DDB42M36 DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB42M18 DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB42M18A 36Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB41M18A 18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB41M36 DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB41M36A 36Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB44M18 DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB44M18A 72Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB451236A 18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
IS61DDB21M18A 18Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM