IS61DDP2B41M18A Description
512Kx36 and 1Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. mon I/O read and write ports.
IS61DDP2B41M18A Key Features
- 512Kx36 and 1Mx18 configuration available
- On-chip Delay-Locked Loop (DLL) for wide data valid window
- mon I/O read and write ports
- Synchronous pipeline read with self-timed late write operation
- Double Data Rate (DDR) interface for read and write input ports
- 2.0 cycle read latency
- Fixed 4-bit burst for read and write operations
- Clock stop support
- Two input clocks (K and K#) for address and control registering at rising edges only
- Two echo clocks (CQ and CQ#) that are delivered simultaneously with data