IS61DDP2B42M18A - 36Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM

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Integrated Silicon Solution

Datasheet Details

Part number	IS61DDP2B42M18A
Manufacturer	Integrated Silicon Solution
File Size	563.36 KB
Description	36Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM
Datasheet	IS61DDP2B42M18A Datasheet
Additional preview pages of the IS61DDP2B42M18A datasheet.

Product details

Description

1Mx36 and 2Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Common I/O read and write ports. Synchronous pipeline read with self-timed late write operation. Double Data Rate (DDR) interface for read and write input ports. 2.0 cycle read latency. Fixed 4-bit burst for read and write operations. Clock stop support. Two input clocks (K and K#) for address and control registering at rising edges only.

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Published: Jul 25, 2016 |