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IS61LPD25636A - 256K x 36/ 512K x 18 9Mb SYNCHRONOUS PIPELINED / DOUBLE CYCLE DESELECT STATIC RAM

General Description

are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications.

Key Features

  • Internal self-timed write cycle.
  • Individual Byte Write Control and Global Write.
  • Clock controlled, registered address, data and control.
  • Burst sequence control using MODE input.
  • Three chip enable option for simple depth expansion and address pipelining.
  • Common data inputs and data outputs.
  • Auto Power-down during deselect.
  • Double cycle deselect.
  • Snooze MODE for reduced-power standby.
  • JTAG Boundary Scan for.

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Datasheet Details

Part number IS61LPD25636A
Manufacturer ISSI (now Infineon)
File Size 253.24 KB
Description 256K x 36/ 512K x 18 9Mb SYNCHRONOUS PIPELINED / DOUBLE CYCLE DESELECT STATIC RAM
Datasheet download datasheet IS61LPD25636A Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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IS61VPD25636A IS61LPD25636A IS61VPD51218A IS61LPD51218A 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM www.DataSheet4U.com ISSI MAY 2005 ® FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Double cycle deselect • Snooze MODE for reduced-power standby • JTAG Boundary Scan for PBGA package • Power Supply LPD: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5% VPD: VDD 2.5V + 5%, VDDQ 2.