IS61LPS204818A Datasheet | ISSI

FEATURES - Internal self-timed write cycle - Individual Byte Write Control and Global Write - Clock controlled, registered address, data and control - Burst sequence control using MODE input - Three chip enable option for simple depth ex- pansion and address pipelining - mon data inputs and data outputs - Auto Power-down during deselect - Single cycle deselect - Snooze MODE for reduced-power standby - Power Supply LPS: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% VPS: Vdd 2.5V + 5%, Vddq 2.5V + 5% - JEDEC 100-Pin TQFP and 165-ball PBGA packages - Lead-free available FAST ACCESS TIME Symbol Parameter tkq Clock Access Time tkc Cycle Time Frequency DESCRIPTION The  ISSI IS61LPS/VPS102436A and IS61LPS/VPS 204818A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for munication and networking applications. The IS61LPS/VPS102436A is organized as 1,048,476 words by 36 bits.The IS61LPS/VPS204818A is organized as 2M-word by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positiveedge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. The byte write operation is performed by using the byte write enable (BWE) input bined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst...