IS61NSCS51236 Datasheet PDF (Synchronous SRAM) | Download Integrated Silicon Solution IS61NSCS51236

IS61NSCS51236 - Synchronous SRAM

This page provides the datasheet information for the IS61NSCS51236, a member of the IS61NSCS25672 Synchronous SRAM family.

Description

Because SigmaRAM is a synchronous device, address, data Inputs, and read/write control inputs are captured on the rising edge of the input clock.

Write cycles are internally self-timed and initiated by the rising edge of the clock input.

Features

JEDEC SigmaRam pinout and package standard.
Single 1.8V power supply (VCC): 1.7V (min) to 1.9V (max).
Dedicated output supply voltage (VCCQ): 1.8V or 1.5V typical.
LVCMOS-compatible I/O interface.
Common data I/O pins (DQs).
Single Data Rate (SDR) data transfers.
Pipelined (PL) read operations.
Double Late Write (DLW) write operations.
Burst and non-burst read and write operations, selectable via dedicated control.

Datasheet Details

Part number	IS61NSCS51236
Manufacturer	Integrated Silicon Solution
File Size	219.50 KB
Description	Synchronous SRAM
Datasheet	IS61NSCS51236 Datasheet
Additional preview pages of the IS61NSCS51236 datasheet.

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Full PDF Text Transcription

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IS61NSCS25672 IS61NSCS51236 Σ RAM 256K x 72, 512K x 36 Features • JEDEC SigmaRam pinout and package standard • Single 1.8V power supply (VCC): 1.7V (min) to 1.9V (max) • Dedicated output supply voltage (VCCQ): 1.8V or 1.

Published: Sep 6, 2013 |