IS61NSCS51236 Description
Because SigmaRAM is a synchronous device, address, data Inputs, and read/write control inputs are captured on the rising edge of the input clock. Write cycles are internally self-timed and initiated by the rising edge of the clock input.
IS61NSCS51236 Key Features
- JEDEC SigmaRam pinout and package standard
- Single 1.8V power supply (VCC): 1.7V (min) to 1.9V (max)
- Dedicated output supply voltage (VCCQ): 1.8V or 1.5V typical
- LVCMOS-patible I/O interface
- mon data I/O pins (DQs)
- Single Data Rate (SDR) data transfers
- Pipelined (PL) read operations
- Double Late Write (DLW) write operations
- Burst and non-burst read and write operations, selectable via dedicated control pin (ADV)
- Internally controlled Linear Burst address sequencing during burst operations