IS61NVP102436A
FEATURES
- 100 percent bus utilization
- No wait cycles between Read and Write
- Internal self-timed write cycle
- Individual Byte Write Control
- Single R/W (Read/Write) control pin
- Clock controlled, registered address, data and control
- Interleaved or linear burst sequence control using
MODE input
- Three chip enables for simple depth expansion and address pipelining
- Power Down mode
- mon data inputs and data outputs
- CKE pin to enable clock and suspend operation
- JEDEC 100-pin TQFP package
- Power supply:
NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%) NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)
- Industrial temperature available
- Lead-free available
DESCRIPTION
The 36 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and munications applications. They are organized as 1M words by 36 bits and 2M words by 18 bits, fabricated with ISSI's advanced CMOS...
