IS61NVVP409618B Datasheet PDF - Integrated Silicon Solution PIPELINE (NO WAIT) STATE BUS SRAM Specs

IS61NVVP409618B - PIPELINE (NO WAIT) STATE BUS SRAM

This page provides the datasheet information for the IS61NVVP409618B, a member of the IS61NLP204836B PIPELINE (NO WAIT) STATE BUS SRAM family.

Datasheet Summary

Description

The 72 Meg product family

Features

100 percent bus utilization.
No wait cycles between Read and Write.
Internal self-timed write cycle.
Individual Byte Write Control.
Single R/W (Read/Write) control pin.
Clock controlled, registered address, data and control.
Interleaved or linear burst sequence control us- ing MODE input.
Three chip enables for simple depth expansion and address pipelining.
Power Down mode.
Common data inputs and data out.

Datasheet Details

Part number	IS61NVVP409618B
Manufacturer	Integrated Silicon Solution
File Size	1.36 MB
Description	PIPELINE (NO WAIT) STATE BUS SRAM
Datasheet	IS61NVVP409618B Datasheet
Additional preview pages of the IS61NVVP409618B datasheet.

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Full PDF Text Transcription

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IS61NLP204836B/IS61NVP/NVVP204836B IS61NLP409618B/IS61NVP/NVVP409618B 2M x 36 and 4M x 18 JULY 2019 72Mb, PIPELINE 'NO WAIT' STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control us- ing MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP, 165-ball PBGA and 119- ball PBGA packages • Power supply: NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) NVP: Vdd 2.5V (± 5%), Vddq 2.

Published: Jul 25, 2016 |