Datasheet Summary
IS61vPS102436A IS61lPS102436A IS61vPS204818A IS61lPS204818A
1Mb x 36, 2Mb x 18 36Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM
JUNE 2010
Features
- Internal self-timed write cycle
- Individual Byte Write Control and Global Write
- Clock controlled, registered address, data and control
- Burst sequence control using MODE input
- Three chip enable option for simple depth ex- pansion and address pipelining
- mon data inputs and data outputs
- Auto Power-down during deselect
- Single cycle deselect
- Snooze MODE for reduced-power standby
- Power Supply
LPS: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% VPS: Vdd 2.5V + 5%, Vddq 2.5V + 5%
- JEDEC 100-Pin TQFP and 165-ball PBGA packages
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