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IS64VPS12836A - 4Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM

This page provides the datasheet information for the IS64VPS12836A, a member of the IS61LPS12832A 4Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM family.

Datasheet Summary

Description

The  ISSI IS61(64)LPS12832A, IS61(64)LPS/VP- S12836A and IS61(64)LPS/VPS25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications.The IS61(64)LPS12832A is organized as 131,072 words by 32 bits.The IS6

Features

  • Internal self-timed write cycle.
  • Individual Byte Write Control and Global Write.
  • Clock controlled, registered address, data and control.
  • Burst sequence control using MODE input.
  • Three chip enable option for simple depth ex- pansion and address pipelining.
  • Common data inputs and data outputs.
  • Auto Power-down during deselect.
  • Single cycle deselect.
  • Snooze MODE for reduced-power standby.
  • Power Supply LPS: V.

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Datasheet preview – IS64VPS12836A

Datasheet Details

Part number IS64VPS12836A
Manufacturer Integrated Silicon Solution
File Size 540.52 KB
Description 4Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM
Datasheet download datasheet IS64VPS12836A Datasheet
Additional preview pages of the IS64VPS12836A datasheet.

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Other Datasheets by Integrated Silicon Solution
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  • IS64C6416AL - 64K x 16 HIGH-SPEED CMOS STATIC RAM
  • IS64LPS12832A - 4Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM
  • IS64LPS12836A - 4Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM
  • IS64LPS25618A - 4Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM
  • IS64LV51216 - (IS61LV51216 / IS64LV51216) 512K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM

Full PDF Text Transcription

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IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A 128K x 32, 128K x 36, 256K x 18 DECEMBER 2013 4 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth ex- pansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Single cycle deselect • Snooze MODE for reduced-power standby • Power Supply LPS: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% VPS: Vdd 2.5V + 5%, Vddq 2.
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