IS42S16128 Overview
The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. 0⋅C to 70⋅C Frequency 125 MHz 100 MHz 83 MHz Speed (ns) 8 10 12 Order Part No.
IS42S16128 Key Features
- Clock frequency: 125 MHz, 100 MHz, 83 MHz
- Two banks can be operated simultaneously and independently
- Single 3.3V power supply
- LVTTL interface
- Programmable burst length
- (1, 2, 4, 8, full page)
- Programmable burst sequence: Sequential/Interleave
- Auto refresh, self refresh
- 1K refresh cycles every 16 ms
- Random column address every clock cycle