21555 - Non-Transparent PCI-to-PCI Bridge

Datasheet Summary

Description

at any time, without notice.

Third-party marks and names are the property of their respective owners.

UNITED STATES AND CANADA Intel Corporation Robert Noyce Bldg.

2200 Mission College Blvd.

Features

The 21555 supports either asynchronous or synchronous primary and secondary clocks. The chip’s I2O-compliant controller uses local memory for Inbound and Outbound List storage with on-chip prefetch and posting buffers, giving lower latency access. The 21555 includes a parallel ROM interface that can be used to attach the Expansion ROM for the subsystem. The ROM interface can also function as a generic 8-bit multiplexed interface with programmable read, write and ready signals to allow attachment.

Intel Corporation

📥 Download Datasheet

Datasheet Details

Part number	21555
Manufacturer	Intel Corporation
File Size	97.43 KB
Description	Non-Transparent PCI-to-PCI Bridge
Datasheet	21555 Datasheet
Additional preview pages of the 21555 datasheet.

📁 Similar Datasheet

Other Datasheets by Intel Corporation

Full PDF Text Transcription

Click to expand full text

product brief 21555 Non-Transparent PCI-to-PCI Bridge Revolutionary Bridge Technology for Intelligent I/O and Embedded Applications Product Highlights s developer.intel.com s Non-Transparent PCI-to-PCI bridge technology for high-performance embedded and intelligent I/O applications Independent address spaces and asynchronous clocks deliver unparalleled application flexibility 64-bit primary and secondary bus interfaces deliver high performance for data-intensive applications Compliant with ACPI and PCI bus power management specifications Secondary bus arbitration support for up to nine bus master devices Evaluation Design Kit speeds time-to-market Fully compliant with Revision 2.

Published: Jun 11, 2007 |