28F128J3A Datasheet | Intel Corporation

Features s s s s s High-Density Symmetrically-Blocked Architecture - 128 128-Kbyte Erase Blocks (128 M) - 64 128-Kbyte Erase Blocks (64 M) - 32 128-Kbyte Erase Blocks (32 M) High Performance Interface Asynchronous Page Mode Reads - 110/25 ns Read Access Time (32 M) - 120/25 ns Read Access Time (64 M) - 150/25 ns Read Access Time (128 M) 2.7 V- 3.6 V VCC Operation 128-bit Protection Register - 64-bit Unique Device Identifier - 64-bit User Programmable OTP Cells Enhanced Data Protection Features Absolute Protection with VPEN = GND - Flexible Block Locking - Block Erase/Program Lockout during Power Transitions s s s s s s Packaging - 56-Lead TSOP Package - 64-Ball Intel® Easy BGA Package Cross-patible mand Support Intel Basic mand Set - mon Flash Interface - Scalable mand Set 32-Byte Write Buffer - 6 µs per Byte Effective Programming Time 12.8M Total Min. Erase Cycles (128 Mbit) 6.4M Total Min. Erase Cycles (64 Mbit) 3.2M Total Min. Erase Cycles (32 Mbit) - 100K Minimum Erase Cycles per Block Automation Suspend Options - Block Erase Suspend to Read - Block Erase Suspend to Program - Program Suspend to Read 0.25 µ Intel® Strata Flash™ Memory Technology Capitalizing on Intel’s 0.25 µ generation two-bit-per-cell technology, second generation Intel® Strata Flash™ memory products provide 2X the bits in 1X the space, with new features for mainstream performance. Offered in 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, these devices bring reliable, two-bit-per-cell storage technology to the flash market segment. Benefits include: more density in less space, high-speed interface, lowest cost-per-bit NOR devices, support for code and data storage, and easy migration to future devices. Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, Intel Strata Flash memory devices take advantage of over one billion units of manufacturing experience since 1987. As a result, Intel Strata Flash ponents are ideal for code and data applications where...