80960CF-16 Datasheet | Intel Corporation

.. PRELIMINARY 80960CF-40, -33, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR EMBEDDED MICROPROCESSOR - Socket and Object Code patible with 80960CA - Two Instructions/Clock Sustained Execution - Four 71 Mbytes/s DMA Channels with Data Chaining - Demultiplexed 32-Bit Burst Bus with Pipelining 32-Bit Parallel Architecture s Four On-Chip DMA Channels - Two Instructions/clock Execution - 71 Mbytes/s Fly-by Transfers - Load/Store Architecture - 40 Mbytes/s Two-Cycle Transfers - Sixteen 32-Bit Global Registers - Data Chaining - Sixteen 32-Bit Local Registers - Data Packing/Unpacking - Manipulates 64-Bit Bit Fields - Programmable Priority Method - 11 Addressing Modes s 32-Bit Demultiplexed Burst Bus - Full Parallel Fault Model - 128-Bit Internal Data Paths to and from - Supervisor Protection Model Registers Fast Procedure Call/Return Model - Burst Bus for DRAM Interfacing - Address Pipelining Option - Full Procedure Call in 4 Clocks - Fully Programmable Wait States On-Chip Register Cache - Supports 8-, 16- or 32-Bit Bus Widths - Caches Registers on Call/Ret - Supports Unaligned Accesses - Minimum of 6 Frames...