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80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS
s High-Performance Embedded Architecture s Built-in Interrupt Controller
— 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz s 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached Instructions s Multiple Register Sets — Sixteen Global 32-Bit Registers — Sixteen Local 32-Bit Registers — Four Local Register Sets Stored On-Chip — Register Scoreboarding s Pin Compatible with 80960SA
— 4 Direct Interrupt Pins — 31 Priority Levels, 256 Vectors s Built-In Floating Point Unit — Fully IEEE 754 Compatible s Easy to Use, High Bandwidth 16-Bit Bus — 25.
80960SB Datasheet
